1. Field of the Invention
This invention relates to a semiconductor memory device having shared bit lines. More particularly, this invention relates to a semiconductor memory device having a plurality of pairs of shared bit lines connected to a SAM type (serial access memory type) read/write system, for example, as used in a video RAM, from which a system data write operation can be carried out to memory cells connected to a selected word line and a selected one of groups of pairs of shared bit lines.
2. Description of the Related Art
Recent increases in the capacities of the semiconductor memory devices has necessitated a corresponding increase in the length of the bit lines. As a result, the stray capacitance of the bit lines to which the selected memory cells are connected can no longer be neglected with respect to the capacitance comprising the memory cells. In this case, considering, for example, an input of data of a memory cell into a corresponding sense amplifier, a slight potential change from the precharge potential is created between the corresponding pairs of bit lines and is amplified by the corresponding sense amplifier. However, as mentioned above, if the stray capacitance of the bit lines is increased, such a slight potential change cannot be satisfactorily created.
Therefore, in the prior art, there has been proposed a semiconductor memory device comprising a plurality of sense amplifiers, a plurality of word lines, a plurality of pairs of shared bit lines, each of the pairs of shared bit lines comprising a pair of inside bit lines extending between the read/write system (e.g., a shift register used in the above SAM type read/write system) and each of the sense amplifiers, and a pair of outside bit lines extending from each of the sense amplifiers to the side opposite to the side of the read/write system, and a plurality of memory cells connected between each of the word lines and each of the pairs of shared bit lines.
Thus, when data in the memory cells connected to the selected word line and the outside bit lines is input to the corresponding sense amplifiers, the inside bit lines are disconnected from the corresponding sense amplifiers by turning OFF the corresponding transfer gates provided between each of the sense amplifiers and each pair of the inside bit lines, so that the stray capacitance of the inside bit lines does not affect the above potential change due to the cell data between the corresponding pair of outside bit lines. Similarly, when data in the memory cells connected to the selected word line and the inside bit lines is input to the corresponding sense amplifiers, the outside bit lines are disconnected from the corresponding sense amplifiers by turning OFF the corresponding transfer gates provided between each of the sense amplifiers and each pair of the outside bit lines. Accordingly, when predetermined data is written from each stage of the shift register into all of the memory cells connected to a selected word line through each pair of bit lines (through each column), all of the sense amplifiers can be driven at the same timing (i.e., before the write data is transferred from the write data transfer means such as the shift register to each pair of bit lines, or after the write data is transferred from the write data transfer means to each pair of bit lines).
However, instead of writing data into all memory cells connected to a selected word line as above-mentioned, sometimes it is necessary to write data only into a part of the memory cells connected to the selected word line. In this case, predetermined data is written from each stage of the shift register into only part of the memory cells connected to the selected word line by selecting one of a plurality of groups of the bit line pairs (by selecting one of a plurality of groups of columns). In such a case, the data write operation can be performed only from each stage of the shift register to the memory cells connected to the selected one of the groups of columns and a read refresh operation is required for the memory cells connected to the remaining groups of the columns where the data write operation is not performed. Namely, the above read refresh operation is required for the memory cells connected to the columns where the data write operation is not performed, by which read refresh operation data stored in the memory cells connected to the columns where the data write operation is not performed is once amplified by the corresponding sense amplifiers, and then the amplified data is rewritten to each of the corresponding memory cells.
In this connection, essentially no problems arise in such a partial write operation for the selected part of memory cells connected to the selected word line and the selected one of groups of pairs of inside bit lines, even if the drive timing of the sense amplifiers belonging to the columns where the data write operation is performed is the same as the drive timing of the sense amplifiers belonging to the columns where the data write operation is not performed (i.e., the read refresh operation is performed).
On the other hand, when the data write operation is carried out for the selected part of memory cells connected to the selected word line and the selected one of groups of pairs of outside bit lines, it is necessary to turn ON the transfer gates provided between each of the sense amplifiers and each pair of the inside bit lines. However, if the above transfer gates are turned ON in order to carry out the above partial write operation before the sense amplifiers are driven, it becomes difficult to create sufficient correct cell data on the corresponding pair of outside bit lines and thus to amplify the above cell data by using the sense amplifiers. This is due to the large stray capacitance including the stray capacitance of the inside and the outside bit lines, which stray capacitance can no longer be neglected with respect to the capacitance comprising each memory cell. Thus, it is necessary to create sufficient cell data on the corresponding pair of outside bit lines while the transfer gates are cut OFF, and thus the length of each pair of bit lines is reduced by a half, to reduce the stray capacitance of each pair of bit lines to by a half. In other words, it is necessary to turn ON the above transfer gates after the cell data created on the corresponding pair of outside bit lines is amplified by the corresponding sense amplifiers, in order to prevent destruction of the cell data created between the pair of outside bit lines corresponding to the columns where the data write operation is not performed (the read refresh operation is performed) from by noise.
However if the write data is transferred to the selected one of the groups of columns where the data write operation is performed after the cell data created on the corresponding pair of outside bit lines is amplified by the corresponding sense amplifiers, a large potential difference due to the cell data is created between the pair of outside bit lines through which the data write operation is performed.
Therefore, in such a case, a problem arises in that it is necessary to provide a very large write amplifier on the write data transfer means side (i.e., the shift register side). Thus, in practice, and considering the requisite area, it has been impossible to perform the above partial write operation, especially into a part of the memory cells connected to the selected word line and the selected one of the groups of outside bit line pairs.